Method and apparatus for sensing resistance values of memory cells

ABSTRACT

A method for sensing the resistance value of a resistor-based memory cell. A current is driven through all unused row lines of a memory array while grounding the row line associated with the selected cell, thereby forcing the current through a comparatively low equivalent resistance formed by the parallel coupling of all unselected memory cells and also through a comparatively high resistance of the selected memory cell. The voltage on a column line corresponding to the selected memory cell is then measured to ground. The voltage level corresponds to either one of two resistance values (i.e., signifying either a logic “HIGH” or a logic “LOW”).

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to the field of resistor-basedmemory circuits. More particularly, it relates to a method foraccurately sensing the resistance value of a resistor-based memory cell,for example, an MRAM magnetic memory cell.

[0003] 2. Description of the Related Art

[0004] A resistor-based memory, such as that depicted in FIG. 1,typically consists of a memory cell array 150 having intersecting rowlines 100 and column lines 110 connected by resistors 120. Aresistor-based memory such as, for example, a magnetic random accessmemory (MRAM), typically includes an array of resistor-based, magneticmemory cells.

[0005] A typical magnetic memory cell includes a layer of magnetic filmin which magnetization is alterable and a layer of magnetic film inwhich magnetization is fixed or “pinned” in a particular direction. Themagnetic film having alterable magnetization may be referred to as adata storage layer and the magnetic film which is pinned may be referredto as a reference layer.

[0006] Typically, the logic state of a magnetic memory cell is indicatedby its resistance which depends on the relative orientations ofmagnetization in its data storage and reference layers. A magneticmemory cell is typically in a low resistance state if the orientation ofmagnetization in its data storage layer is substantially parallel to theorientation of magnetization in its reference layer. A magnetic memorycell is typically in a high resistance state if the orientation ofmagnetization in its data storage layer is substantially anti-parallelto the orientation of magnetization in its reference layer.

[0007] A magnetic memory cell is usually written to a desired logicstate by applying external magnetic fields that rotate the orientationof magnetization in its data storage layer. Typically, the orientationof magnetization in the data storage layer aligns along an axis of thedata storage layer that is commonly referred to as its easy axis.External magnetic fields are applied to flip the orientation ofmagnetization in the data storage layer along its easy axis to either aparallel or anti-parallel orientation with respect to the orientation ofmagnetization in the reference layer depending on the desired logicstate.

[0008] When the orientation of magnetization is flipped, the resistanceof the memory cell is altered between two different values. Oneresistance value, e.g., the higher value, may be selected to signify alogic “HIGH” while the other resistance value, e.g., the lower value,may be selected to signify a logic “LOW.”

[0009] The value of each memory cell is determined by measuring theresistance value of the cell so as to determine whether the cellcorresponds to a logic “HIGH” or logic “LOW.” This measuring process hadbeen made difficult due to several factors.

[0010] First, there is typically little to no isolation between memorycells. For example, turning to FIG. 2, which depicts a smaller portionof the FIG. 1 memory array, if an array consists of 1024 rows and 1024columns, i.e., approximately 1 million cells, and each cell contains aresistance of 1.2 MΩ or 800 KΩ, depending on its logic state, themeasured resistance when all rows and all columns, except for thoseassociated with the selected cell, are respectively shorted together(e.g., during a read operation as depicted by dotted lines in FIG. 1)will be approximately 1 Ω, leaving very little isolation between cells.Low isolation renders the measuring of the resistance value of aparticular memory cell difficult. Currently available solutions to theisolation problem include inserting a metal oxide semiconductor fieldeffect transistor (MOSFET) or a diode in the memory cell in order tochange the resistance value, making it easier to detect. This solutionis overly complex, increases the size of the memory cell and complicatesthe manufacturing process.

[0011] Turning now to FIG. 3, a typical resistance sensing circuit isdepicted. The unknown parallel paths are represented by an equivalentresistance 300 of approximately 1 KΩ. The resistive element 210 of theselected cell is 1.2 MΩ. The column line 230 and the unused row linesare maintained at some known voltage. The current through the resistance300 of the unused row lines is kept as close to zero as practical bymaintaining a zero difference of potential across the resistance 300.The voltage across the 1.2 MΩ resistance 210 to ground (at node A) isthen read. One of the problems associated with the FIG. 3 circuit isthat it is very difficult to maintain a zero difference of potentialacross the unused resistors 300, and, therefore, there is always anon-zero current flow through resistance 300, thus affecting the voltagereading at node A and making the reading of resistance 210 difficult andunreliable. For example, if the difference of potential across points Aand B, that is, across resistor 300, is 2 mV, then the current throughresistance 300 is approximately 2 μA and if the voltage at node A toground is maintained at e.g., 2V, the current through resistance 210 isapproximately 1.7 μA. Since the voltage differences between points A andB are not stable, the current through resistor 300 varies, therebyposing serious problems when reading the contents of a memory cell.

[0012] Another concern is that since the resistance values of each cellare so high (e.g., approximately 1 MΩ), large (RC) time constants willbe experienced in the parasitic paths (i.e., for the unused cells). Asknown in the art, these large RC constants increase the time required toread out the contents of a memory cell. For example, the inherentdischarge times can be undesirably long when all of the rows, except forthe one being read out, and columns are pre-charged to some voltage.Furthermore, large resistance variations are typically experienced fromcell to cell depending upon the processing employed duringmanufacturing, thus leading to less reliability during the measurementprocess. At least for those reasons described above, a simplified, morereliable method of sensing the resistance value of a resistor-basedmemory cell is desirable.

SUMMARY OF THE INVENTION

[0013] The present invention overcomes the problems associated with theprior art and provides a simplified and reliable method for sensing theresistance value of a resistor-based memory cell. A current is driventhrough all unused row lines of a memory array while grounding the rowline associated with the selected cell, thereby forcing the currentthrough a comparatively low equivalent resistance (e.g., 1 KΩ) and alsothrough a comparatively high resistance (e.g., 1.2 MΩ or 800 KΩ) of theselected memory cell. The voltage on the column line corresponding tothe selected memory cell is then measured to ground. The voltage levelcorresponds to either one of two resistance values (i.e., signifyingeither a logic “HIGH” or a logic “LOW”).

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The foregoing and other advantages and features of the inventionwill become more apparent from the detailed description of preferredembodiments of the invention given below with reference to theaccompanying drawings in which:

[0015]FIG. 1 illustrates a typical resistor-based memory cell array;

[0016]FIG. 2 illustrates a desired cell of the FIG. 1 memory cell array;

[0017]FIG. 3 illustrates a typical resistance sensing circuit;

[0018]FIG. 4 illustrates a resistance sensing circuit in accordance witha first exemplary embodiment of the invention;

[0019]FIG. 5 illustrates a resistance sensing circuit in accordance withthe first exemplary embodiment of the invention;

[0020]FIG. 6 depicts a flowchart of an operational flow in accordancewith an exemplary embodiment of the invention;

[0021]FIG. 7 illustrates an RC circuit for use with sensing resistancein accordance with a second exemplary embodiment of the invention;

[0022]FIG. 8 is a graphical representation of voltage levels measuredusing the FIG. 7 circuit;

[0023]FIG. 9 illustrates a control system in accordance with a thirdexemplary embodiment of the invention;

[0024]FIG. 10 illustrates reference columns for use with a memory arrayin accordance with a fourth exemplary embodiment of the invention;

[0025]FIG. 11 illustrates a reference voltage detecting circuit inaccordance with a fifth exemplary embodiment of the invention;

[0026]FIG. 12 illustrates a sense amplifier for use with the exemplaryembodiments of the invention;

[0027]FIG. 13 illustrates a schematic diagram of the FIG. 12 senseamplifier; and

[0028]FIG. 14 illustrates a clamp circuit for use with a memory array inaccordance with a sixth exemplary embodiment of the invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0029] The present invention will be described as set forth in exemplaryembodiments illustrated in FIGS. 4-14. Other embodiments may be realizedand other changes may be made to the disclosed embodiments withoutdeparting from the spirit or scope of the present invention.

[0030]FIG. 4 illustrates a resistance sensing circuit for sensing theresistance value of a resistor-based memory cell, in accordance with afirst exemplary embodiment of the invention. A current source 400delivers a small current (e.g., 1 mA) to the memory array 150 such thateach of the unused row lines 450 of the memory array 150 conductsapproximately 1 μA (i.e., assuming a 1024×1024 array). The row line 500associated with a selected cell 460 is driven to ground. Each of theunused row lines 450 coupled to the column line 230 associated with theselected cell 460 is shorted to the others so that an equivalentresistance of approximately 1 KΩ is read at column line 230.

[0031] Turning to FIG. 5, an equivalent circuit schematic diagram of theFIG. 4 resistance sensing circuit is depicted. The 1.2 MΩ or 800 KΩresistance of the selected cell 460 is coupled between the column line230 and the row line 500 which is driven to ground. For purposes ofdiscussion, it is assumed that the resistance value for cell 460 is 1.2MΩ. The equivalent resistance 300 of the unused memory cells isrepresented as 1 KΩ in series with the 1.2 MΩ resistance of the desiredcell 460. The current source 400 drives approximately 1 μA through eachof the unused row lines 450 so that a voltage drop appears at each ofthe resistors 300, 210. The value of the voltage read across theresistance of the desired cell 460 is fed to a sense amplifier 480 wherea determination is made as to the logic value of the selected memorycell 460. That is, unlike the prior art configurations of FIGS. 2-3, theFIG. 4 embodiment drives a constant, known current through bothresistances 300 and 210, thereby making the measurement of resistance210 both easier and more reliable.

[0032] Turning now to FIG. 6, a flowchart of an operational flow of anexemplary resistance memory containing the memory cell reading circuitof FIGS. 4, 5 is depicted. The flow begins at process segment 6000. Atsegment 6100, a cell 460 is selected. One side of the resistor 210 ofthe selected memory cell 460 is grounded by grounding the associatedwordline (row) at segment 6200. At segment 6300, a current is driventhrough all unselected row lines. At segment 6400, a voltage measurementis taken from the column line 230 that is associated with the selectedmemory cell 460 to ground. The measured voltage is compared with areference voltage at segment 6500 to determine the cell resistance valueand, ultimately, the logic value stored in the cell 460. The processflow ends at segment 6600.

[0033] Turning now to FIG. 7, an RC circuit for use with a resistancesensing circuit is depicted in accordance with a second embodiment ofthe invention. The FIG. 7 circuit may be employed to carry out thecurrent driving described above with reference to segment 6300 of theFIG. 6 flowchart. The FIG. 7 circuit may be desirable in lieu of aconstant current source when the rate of charging of the array 150 iscomparatively slow. For example, if the capacitance of the column line230 is 500 fF and the current being driven by constant current source400 is approximately 1 μA, since i=C(dv/dt), the rate of charging thearray 150 is 2 mV/ns (i.e., very slow).

[0034] An alternative to driving these very small constant currentsthrough the array 150 is to charge the array 150 up to a predeterminedvoltage. In the FIG. 5 schematic, the equivalent resistance 300 iscoupled to the resistance 210 of the selected cell 460; however, in theFIG. 7 embodiment, the capacitance 610 of the row line 500 associatedwith the selected cell 460 and the capacitance 600 of the column line230 associated with the selected cell 460 form two RC circuits. Inaccordance with the second embodiment of the invention, rather thanforcing a current through the array 150 with a constant current source(as in FIG. 5), the array is charged to a predetermined voltage (e.g.,by charging both capacitors 600 and 610 to 1V), then switches 740 and750 are closed and capacitors 600, 610 are respectively dischargedacross resistors 300, 210. The voltage measured at point C is then fedinto sense amplifier 480 where it is compared with a reference voltagein order to determine the value of the resistor 210, the referencevoltage being of a value halfway between a voltage expected for an 800KΩ resistor and a 1.2 MΩ resistor.

[0035] Turning now to FIG. 8, exemplary discharge curves for a 1.2 MΩresistor and an 800 KΩ resistor as two possible resistance values for acell are depicted. Here the voltages of the two resistors are monitoredat a predetermined time period (t₁). The measured voltages will differproportionally at time t₁, depending upon the value of the resistance(e.g., 800 KΩ vs. 1.2 MΩ). The difference in voltage ΔV is used todetermine the logic level being stored in the memory cell 460.

[0036] Turning to FIG. 9, a control circuit is depicted in accordancewith a third exemplary embodiment of the invention. A constant currentsource 400 is coupled to memory array 150 in the manner shown in theFIG. 5 embodiment. A monitor 810 is coupled to a column line (e.g., 230)associated with a predetermined memory cell (e.g., 460) of array 150 fordetecting the voltage being measured at the column line 230. Monitor 810contains, e.g., a comparator 905. An input of comparator 905 receivesthe voltage on column line 230 and a second input of comparator 905receives a reference voltage V_(ref). If the voltage being measured atthe selected memory cell (e.g., at 230), or cells, is above or below apredetermined value (V_(ref)), the monitor 810 sends a control signal toconstant current source 400 to increase or decrease the current levelbeing delivered to the array 150 and being driven through the unused rowlines of the memory array 150. For example, if in the FIG. 4 schematicdiagram, a voltage corresponding to a 1.2 MΩ resistor falls below apredetermined threshold level (e.g., 1.0 V), the FIG. 9 control systemensures that the output level of the constant current source 400 isincreased by an amount sufficient to maintain the voltage reading acrossthe 1.2 MΩ resistors at the predetermined threshold level (e.g., 1.0 V).

[0037] Turning now to FIG. 10, reference columns 1150, 1160 for use withthe sense reference amplifiers 480 (of FIGS. 4 and 5) are depicted. Eachof the reference columns 1150, 1160 is coupled to one end of each of aplurality of reference resistors 1170 and 1180. The other end ofreference resistors 1170 and 1180 is coupled to the row lines of thememory array 150. The resistance values of resistors 1170 are the sameand the resistance values of resistors 1180 are the same. That is, acolumn of reference “1” is written into the cells associated with column1150 and a column of reference “0” is written into the cells associatedwith column 1160.

[0038] The reference resistors 1170 and 1180 are then converted into areference voltage level (as will be described in connection with FIG.11) and fed into one input of a sense amplifier 480 for determining thelogic levels of a selected cell 460. Resistance values may vary over thespan of a given memory array and the transmission of a reference value(or voltage) across a memory array 150 for comparison with a selectedmemory cell 460 can detrimentally affect the integrity of the referencevalue and compromise the comparison. Therefore, it is recommended thatthe frequency and placement of the reference columns 1150, 1160 in thearray 150 be whatever is practical depending upon the operatingconditions and spatial considerations (e.g., noise from the substrate,decoders, size of the array, etc.) of the memory array 150.

[0039] Turning now to FIG. 11, a reference voltage detecting circuit isdepicted for determining a reference voltage from reference columns1150, 1160 (of FIG. 10), in accordance with a fourth exemplaryembodiment of the invention. A constant current (e.g., 1 μA) is driventhrough each of the reference resistances 1020, 1030 by a respectivecurrent source 1000, 1010. It should be apparent that current sources1000, 1010 may be combined into a single current source. The referencevoltage is measured on reference line 1050 and is intended to behalf-way between a voltage corresponding to a “0” reference and avoltage corresponding to a “1” reference. As shown in FIG. 12, thereference voltage value measured at line 1050 is then fed into an inputof a sense amplifier 480 where it is compared with a voltage measuredacross a resistor in a selected cell 460. If the measured voltage isgreater than the reference voltage, a logic HIGH (e.g., “1”) is measuredin the cell. Alternatively, if the measured voltage is lower than thereference voltage, a logic LOW (e.g., “0”) is measured in the cell. Itshould be apparent that the opposite conditions/states may hold true ifso desired by the circuit designer.

[0040] The sense amplifier 480 has a first input line 230 for receivinga sense voltage measured across a resistor 210 of a selectedresistor-based memory cell 460. Input line 230 is the column line of theselected cell 460. The first input line 230 is also referred to as“Digit” in the interest of being consistent with conventional dynamicrandom access memory (DRAM) terminology. Sense amplifier 480 also has asecond input line 1050 for receiving a reference voltage from areference voltage detecting circuit (e.g., as in FIG. 11). The secondinput line 1050 is referred to as “Digit*” in order to be consistentwith DRAM terminology. The sense amplifier has two output lines I/O 1105and I/O* 1100. The purpose of output lines I/O 1105 and I/O* 1100 iswell known in the art and, therefore, only a brief description of theirfunction will be described in connection with FIG. 13.

[0041] Turning now to FIG. 13, an exemplary sense amplifier 480 for usewith the described embodiments of the invention is depicted. Theoperation of sense amplifiers, in general, is well known in the art, andtherefore, only a brief description will be provided herein. Firstrespective terminals of p-type MOSFETs 1305 and 1310 are connected toV_(DD). The gate of MOSFET 1310 is coupled to I/O*, a second terminal ofMOSFET 1305, a first terminal of MOSFET 1315, a first terminal of MOSFET1320, a first terminal of MOSFET 1345 and the gate of MOSFET 1325. Thegate of MOSFET 1305 is coupled to I/O, a second terminal of MOSFET 1310,a second terminal of MOSFET 1315, a first terminal of MOSFET 1325, afirst terminal of MOSFET 1335 and the gate of MOSFET 1320. The gate ofMOSFET 1315 is coupled to “Latch.” A second terminal of MOSFET 1345 iscoupled to a first terminal of MOSFET 1350 and the gate of MOSFET 1345is coupled to “Digit.” A second terminal of MOSFET 1350 is coupled toground. A second terminal of MOSFET 1335 is coupled to a first terminalof MOSFET 1340 and the gate of MOSFET 1335 is coupled to “Digit*.” Thegates of MOSFET 1350 and MOSFET 1340 are coupled to “Sense.” Secondrespective terminals of MOSFET 1320 and MOSFET 1325 are coupled togetherand also coupled to a first terminal of MOSFET 1330. A second terminalof MOSFET 1330 is coupled to ground and the gate of MOSFET 1330 iscoupled to “Latch.”

[0042] Both “Sense” and “Latch” are started at logic LOW. The I/O linesare equilibrated and MOSFET 1315 is activated. When “Sense” is madelogic “HIGH,” the sense amplifier 480 begins sensing the resistance ofthe selected cell 460. When “Latch” goes logic “HIGH” the I/O lines aredriven to V_(DD) and ground. Also, since “Sense” is logic “HIGH,” I/Ocannot go all the way to V_(DD). When “Sense” goes logic “LOW,” and“Latch” is logic “HIGH,” I/O goes all the way to V_(DD,) and there is nostatic power dissipation.

[0043] Referring now to FIG. 14, a current limiting circuit which may beused with the memory array current driver 400 is depicted. A clamptransistor 1300 is placed between a constant current source 400 and thememory array 150 such that when biasing the input current to the memoryarray 150, any excess current is diverted to ground rather than thearray 150. This circuit prevents overcurrent to the array 150 which maycause problems including inadvertently rewriting of the values of thememory cells.

[0044] The present invention provides a method by which the resistancevalue of a resistor-based memory cell is sensed in a reliable mannerthat enables the determination of the logic value stored by the cell. Asimple circuit is disclosed employing a current source 400 that drives acurrent through both the unused row lines and the resistor of theselected memory cell 460 and to ground. The voltage across the resistorof the selected cell 460 is measured from the column line 230 associatedwith the selected cell 460 to ground. The measured voltage is fed into asense amplifier 480 where it is compared with a reference voltage and adetermination is made as to the logic level being stored by the memorycell 460.

[0045] In another embodiment, the capacitance of the row line 500 andcolumn line 230 associated with the selected cell are charged to apredetermined voltage. The capacitors arc then discharged across boththe combined resistance 300 of the unselected cell, and the resistor 210associated with the selected cell 460, thereby replacing the constantcurrent source 400.

[0046] Additionally, a feedback control loop may be utilized to monitorthe voltage being measured at the resistor 210 associated with theselected cell 460, such that if the voltage deviates from apredetermined value, the current being delivered to the memory array maybe increased or decreased. Another way to limit the current delivered tothe memory array 150 is to introduce a current clamp 1300 between thecurrent source 400 and the memory array 150.

[0047] While the invention has been described in detail in connectionwith preferred embodiments known at the time, it should be readilyunderstood that the invention is not limited to the disclosedembodiments. Rather, the invention can be modified to incorporate anynumber of variations, alterations, substitutions or equivalentarrangements not heretofore described, but which are commensurate withthe spirit and scope of the invention. For example, although theinvention has been described in the context of MRAM, it may be used forsensing the resistance value of any system in which maintaining aresistance level is critical. In addition, while specific values ofcurrent, voltage capacitance and resistance have been used to describethe illustrated embodiments, it should be apparent that different valuesmay be used in their place without deviating from the scope of thedescribed embodiments. Accordingly, the invention is not limited by theforegoing description or drawings, but is only limited by the scope ofthe appended claims.

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:
 1. A method for sensing resistance of cells of amemory array, the method comprising: passing a current through each of aplurality of resistors associated with unselected memory cells of saidmemory array; passing said current through a resistor associated with aselected memory cell of said memory array; and measuring a voltage dropacross said resistor associated with said selected memory cell todetermine a resistance value of said resistor.
 2. The method of claim 1,wherein said first act of passing comprises driving said current througheach of a plurality of row lines associated with said unselected memorycells.
 3. The method of claim 1, wherein said second act of passingcomprises grounding a row line associated with said selected memorycell.
 4. The method of claim 3, wherein said act of measuring comprisesmeasuring said voltage drop across a column line associated with saidselected memory cell and ground.
 5. The method of claim 1, wherein saidfirst act of passing comprises driving said current with a constantcurrent source.
 6. The method of claim 1, wherein said first act ofpassing comprises discharging a capacitor across each of said unselectedmemory cells and wherein said second act of passing comprisesdischarging a capacitor across said selected memory cell so as togenerate a current through said unselected and selected memory cells. 7.The method of claim 6, wherein said act of discharging comprises:discharging a voltage stored by capacitance of a column line associatedwith said selected memory cell across each of said plurality ofresistors associated with said unselected memory cells; and discharginga voltage stored by capacitance of a row line associated with saidselected memory cell across said resistor associated with said selectedmemory cell.
 8. The method of claim 1 further comprising comparing saidmeasured voltage drop with a reference voltage to determine saidresistance value.
 9. The method of claim 8, wherein said act ofcomparing comprises sending said measured voltage to one input of asense amplifier where it is compared with said reference voltage. 10.The method of claim 9 further comprising determining a logic levelassociated with said selected memory cell based upon results of said actof comparing.
 11. The method of claim 1 further comprising modifyingsaid current depending upon said voltage drop.
 12. The method of claim11, wherein said act of modifying comprises: receiving said voltage dropat a first input of a comparator; receiving a reference voltage at asecond input of said comparator; and sending a control signal from saidcomparator to a current source for adjusting said current.
 13. Themethod of claim 1 further comprising limiting said current to apredetermined value before said current passes through said memoryarray.
 14. The method of claim 13, wherein said act of limitingcomprises limiting said current with a clamp transistor.
 15. The methodof claim 9, wherein said act of comparing comprises receiving at saidsense amplifier said reference voltage as detected by a referencevoltage detecting circuit.
 16. A circuit for sensing resistance of cellsof a memory array, the circuit comprising: a plurality of resistorsassociated with said memory array such that when a memory cell of saidarray is selected, said plurality of resistors, except for a resistorassociated with said selected memory cell, are connected in parallel,said resistor associated with said selected memory cell being in serieswith said plurality of resistors connected in parallel; and a currentsource coupled to said memory array for driving a current through saidplurality of resistors connected in parallel and said resistorassociated with said selected memory cell.
 17. The circuit of claim 16further comprising a voltage measurement point which, when measured,provides a value of a voltage across said resistor associated with saidselected memory cell.
 18. The circuit of claim 16, wherein said currentsource comprises a constant current source.
 19. The circuit of claim 16,wherein said current source comprises a capacitor discharged across eachof said plurality of resistors so as to generate a current through saidresistors.
 20. The circuit of claim 19, wherein said current sourcecomprises a capacitor respectively coupled to each of said plurality ofresistors connected in parallel for discharging a stored voltage acrosseach of said plurality of resistors connected in parallel; and acapacitor coupled to said resistor associated with said selected memorycell for discharging a stored voltage across said resistor associatedwith said selected memory cell.
 21. The circuit of claim 16, whereineach of said plurality of resistors associated with said memory arrayare coupled between a corresponding row line and a corresponding columnline that define a memory cell of said memory array.
 22. The circuit ofclaim 16, wherein said current source is coupled to each row line ofsaid memory array.
 23. The circuit of claim 22, wherein a row lineassociated with said selected memory cell is grounded thereby creating apath for said current through said selected memory cell.
 24. The circuitof claim 17, wherein said voltage measurement point comprises a columnline associated with said selected memory cell.
 25. The circuit of claim17 further comprising a comparator coupled to said voltage measurementpoint for comparing said voltage with a reference voltage to determine aresistance value of said resistor associated with said selected memorycell.
 26. The circuit of claim 25, wherein said comparator comprises asense amplifier.
 27. The circuit of claim 26, wherein an input of saidsense amplifier is coupled to a column line associated with saidselected memory cell for receiving said voltage.
 28. The circuit ofclaim 16, wherein each of said plurality of resistors associated withsaid memory cell array has a logic level associated with it dependingupon a resistance value of a given resistor.
 29. The circuit of claim16, wherein said memory array comprises a random access memory (RAM).30. The circuit of claim 29, wherein said RAM comprises a magnetic RAM.31. The circuit of claim 17 further comprising a voltage monitor formonitoring said voltage, said voltage monitor also being coupled to saidcurrent source for modifying said current depending upon said voltage.32. The circuit of claim 31, wherein said voltage monitor comprises: acomparator having a first input coupled to said voltage measurementpoint and a second input coupled to a reference voltage, said comparatorhaving an output coupled to said current source for transmitting acontrol signal to modify said current depending upon said voltage. 33.The circuit of claim 16 further comprising a current limiter coupledbetween said current source and said plurality of resistors for limitingsaid current driven through said plurality of resistors.
 34. The circuitof claim 33, wherein said current limiter comprises a clamp transistor.35. The circuit of claim 25 further comprising a reference voltagedetecting circuit coupled to said comparator for transmitting saidreference voltage.
 36. The circuit of claim 35, wherein said referencevoltage detecting circuit comprises a current source coupled to at leasttwo parallel resistors, each of said parallel resistors having areference value associated with a logic state that is opposite the logicstate of the other resistor.
 37. A circuit for sensing resistance ofcells of a memory array, the circuit comprising: a plurality ofresistors associated with said memory array such that when a memory cellof said array is selected, the plurality of resistors, except for aresistor associated with said selected memory cell, is connected to forma first equivalent resistance, said resistor associated with saidselected memory cell being in series with said first equivalentresistance; and a current source coupled to said memory array fordriving a current through said first equivalent resistance and saidresistor associated with said selected memory cell.
 38. A control systemfor sensing resistance of cells of a memory array, the systemcomprising: a memory array comprising a plurality of resistors, each ofsaid resistors corresponding to a memory cell of said array; a currentsource coupled to said memory array for passing a current through saidplurality of resistors; and a monitor for monitoring a voltage levelmeasured across at least a selected one of said plurality of resistorsin said memory array, such that if said voltage level deviates from apredetermined value, said current is adjustable.
 39. The system of claim38 further comprising a current limiter coupled between said memoryarray and said current source for limiting said current.
 40. The systemof claim 38, wherein said plurality of resistors are coupled such thatwhen a memory cell of said array is selected, said plurality ofresistors, except for a resistor associated with said selected memorycell, are connected in parallel, said resistor associated with saidselected memory cell being in series with said plurality of resistorsconnected in parallel.
 41. The system of claim 38, wherein said currentsource comprises a constant current source.
 42. The system of claim 40,wherein said current source comprises a capacitor discharged across eachof said plurality of resistors so as to generate a current through saidresistors.
 43. The system of claim 42, wherein said current sourcecomprises a capacitor respectively coupled to each of said plurality ofresistors connected in parallel for discharging a stored voltage acrosseach of said plurality of resistors connected in parallel; and acapacitor coupled to said resistor associated with said selected memorycell for discharging a stored voltage across said resistor associatedwith said selected memory cell.
 44. The system of claim 40, wherein eachof said plurality of resistors associated with said memory cell arrayare coupled between a corresponding row line and a corresponding columnline that define a memory cell of said memory array.
 45. The system ofclaim 38, wherein said current source is coupled to each row line ofsaid memory cell array.
 46. The system of claim 38, wherein a row lineassociated with said selected memory cell is coupled to ground therebycreating a path for said current through said selected memory cells. 47.The system of claim 38, wherein said memory array comprises a randomaccess memory (RAM).
 48. The system of claim 47, wherein said RAMcomprises a magnetic RAM.
 49. A control system for sensing resistance ofcells of a memory array, the system comprising: a memory arraycomprising a plurality of resistors, each of said resistorscorresponding to a memory cell of said memory array; a current sourcecoupled to said memory array for passing a current through saidplurality of resistors associated with memory cells; and a currentlimiting device coupled between said current source and said memoryarray for limiting said current to said memory array.
 50. The system ofclaim 49 further comprising a monitor coupled between said memory arrayand said current source for monitoring a voltage level measured acrossat least a selected one of said plurality of resistors in said memoryarray, such that if said voltage level deviates from a predeterminedvalue, said current is adjustable.
 51. The system of claim 49, whereinwhen a memory cell of said array is selected, said plurality ofresistors, except for a resistor associated with said selected memorycell, is connected in parallel, said resistor associated with saidselected memory cell being in series with said plurality of resistorsconnected in parallel.
 52. The system of claim 49, wherein said currentlimiting device comprises a clamping transistor for drawing excessivecurrent from a conductor coupling said current source and said memoryarray.
 53. The system of claim 49, wherein said memory array comprises arandom access memory (RAM).
 54. The system of claim 53, wherein said RAMcomprises a magnetic RAM.
 55. A memory array comprising: a firstreference cell containing a first resistor of a first resistance value;a second reference cell containing a second resistor of a secondresistance value, wherein a current source is coupled to said first andsecond reference cells for passing a current through said first andsecond reference cells, and wherein said first and second referencecells are coupled to each other so as to enable a detection of areference voltage to be fed into an input of a comparator for comparingsaid reference voltage with a voltage sensed from a selected memory cellof said memory array.
 56. The memory array of claim 55, wherein saidcomparator comprises a sense amplifier.
 57. The memory array of claim55, wherein said first and second resistors are connected in parallel,each of said first and second resistors respectively passing a currentdriven by said current source, wherein said reference voltage ismeasured at a point between said current source and said resistors. 58.The memory array of claim 55, further comprising at least two referencecolumns, a first one of which contains a first plurality of referencecells including said first reference cell, a second one of whichcontains a second plurality of reference cells including said secondreference cell.
 59. The memory array of claim 55, wherein said memoryarray comprises a random access memory (RAM).
 60. The memory array ofclaim 55, wherein said RAM comprises a magnetic RAM.